US 11,798,638 B2
Mitigating neighbor interference to select gates in 3D memory
Xiang Yang, Santa Clara, CA (US); Kou Tei, San Jose, CA (US); and Ohwon Kwon, Pleasanton, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,218.
Prior Publication US 2023/0101019 A1, Mar. 30, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 25/065 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC G11C 16/3427 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus comprising:
a control circuit configured to connect to a three-dimensional memory structure comprising NAND strings, each NAND string comprising memory cells and a drain side select gate, the three-dimensional memory structure comprising bit lines, each drain side select gate of a NAND string associated with a bit line, the three-dimensional memory structure comprising word lines connected to memory cells on the NAND strings, the control circuit configured to:
pre-charge a first set of the bit lines to a first voltage;
pre-charge a second set of the bit lines to a second voltage that is greater than the first voltage;
float the second set of the bit lines after charging to the second voltage;
increase the voltage on the first set of the bit lines from the first voltage to a third voltage while the second set of the bit lines are floating to couple up the voltages on the second set of the bit lines to a voltage greater than the second voltage; and
apply a program voltage greater than zero volts to a selected word line while the first set of the bit lines are at the third voltage and while the voltages on the second set of the bit lines are at the voltage greater than the second voltage, wherein the selected word line is connected to a memory cell on each of the NAND strings.