| US 11,798,631 B2 | ||
| Transfer latch tiers | ||
| Iris Lu, Fremont, CA (US); and Tai-Yuan Tseng, Milpitas, CA (US) | ||
| Assigned to SanDisk Technologies LLC, Addison, TX (US) | ||
| Filed by SanDisk Technologies LLC, Addison, TX (US) | ||
| Filed on Oct. 21, 2021, as Appl. No. 17/507,606. | ||
| Prior Publication US 2023/0130365 A1, Apr. 27, 2023 | ||
| Int. Cl. G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01) | ||
| CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] | 17 Claims |
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1. An apparatus, comprising:
an array of non-volatile memory cells formed along a plurality of bit lines, the plurality of bit lines arranged in a plurality of columns; read and write circuitry, comprising:
a plurality of data latches, each data latch of the plurality of data latches connected to a bit line of the plurality of bit lines and arranged in a same column as the bit line; and
a plurality of transfer latches, each transfer latch of the plurality of transfer latches connected to a data latch of the plurality of data latches and arranged in a same column as the data latch, wherein each column of the plurality of columns comprises N bit lines, N data latches, and N transfer latches and N is an integer greater than one;
circuitry connected to transfer latches of a first column of the plurality of columns and a subset of transfer latches of a second column of the plurality of columns and configured to transfer a word of M bits to and from the transfer latches of the first column and the subset of transfer latches of the second column, wherein M is an integer greater than N; circuitry connected to the transfer latches of the first column and data latches of the first column and configured to transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and circuitry connected to the transfer latches of the second column and data latches of the second column and configured to transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches, wherein the circuitry connected to the transfer latches of the second column and data latches of the second column is further configured to transfer a portion of another word from remaining transfer latches of the second column to data latches of the second column that are connected to the remaining transfer latches of the second column. |