US 11,798,620 B2
Apparatuses including multi-level memory cells and methods of operation of same
Innocenzo Tortorelli, Cernusco Sul Naviglio (IT); Russell L. Meyer, Boise, ID (US); Agostino Pirovano, Milan (IT); Andrea Redaelli, Casatenovo (IT); Lorenzo Fratin, Buccinasco (IT); and Fabio Pellizzer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 1, 2022, as Appl. No. 17/816,612.
Application 17/816,612 is a continuation of application No. 16/436,734, filed on Jun. 10, 2019, granted, now 11,482,280.
Application 16/436,734 is a continuation of application No. 15/231,518, filed on Aug. 8, 2016, granted, now 10,446,226, issued on Oct. 15, 2019.
Prior Publication US 2022/0366974 A1, Nov. 17, 2022
Int. Cl. G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01)
CPC G11C 11/5678 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 2013/005 (2013.01); G11C 2013/0052 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/71 (2013.01); G11C 2213/76 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method, comprising:
selecting a voltage of a write pulse;
selecting a polarity of the write pulse; and
applying the write pulse having the voltage and polarity across a memory cell, wherein the write pulse writes a logic state to the memory cell, wherein the logic state is based, at least in part, on the voltage and polarity of the write pulse, wherein the logic state of the memory cell corresponds to multiple bits, wherein the multiple bits of data are stored in different physical locations in the memory cell, wherein a first bit of the multiple bits is stored in a selector device of the memory cell and a second bit of the multiple bits is stored in a memory element of the memory cell.