CPC G11C 11/5678 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 2013/005 (2013.01); G11C 2013/0052 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/71 (2013.01); G11C 2213/76 (2013.01)] | 15 Claims |
1. A method, comprising:
selecting a voltage of a write pulse;
selecting a polarity of the write pulse; and
applying the write pulse having the voltage and polarity across a memory cell, wherein the write pulse writes a logic state to the memory cell, wherein the logic state is based, at least in part, on the voltage and polarity of the write pulse, wherein the logic state of the memory cell corresponds to multiple bits, wherein the multiple bits of data are stored in different physical locations in the memory cell, wherein a first bit of the multiple bits is stored in a selector device of the memory cell and a second bit of the multiple bits is stored in a memory element of the memory cell.
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