CPC G06N 3/065 (2023.01) [G06F 3/061 (2013.01); G06F 3/0688 (2013.01); G06F 17/16 (2013.01); G06N 3/048 (2023.01); G06N 3/08 (2013.01); G11C 11/5642 (2013.01); G11C 13/004 (2013.01); G11C 16/0425 (2013.01); G11C 16/28 (2013.01); G11C 2211/563 (2013.01); G11C 2213/15 (2013.01)] | 16 Claims |
1. A method comprising:
receiving a first voltage;
multiplying the first voltage by a coefficient to generate a second voltage;
applying the first voltage to one of a gate of a reference transistor and a gate of a selected memory cell;
applying the second voltage to the other of the gate of the reference transistor and the gate of the selected memory cell; and
using the reference transistor in a sense operation to determine a value stored in the selected memory cell.
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