US 11,797,747 B1
Identifying redundant logic based on clock gate enable condition
Matthew David Eaton, Stow-cum-Quy (GB); George Simon Taylor, Round Rock, TX (US); Zhuo Li, Austin, TX (US); James Youren, Cambridge (GB); and Ji Xu, Cambridge (GB)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 24, 2021, as Appl. No. 17/410,837.
Claims priority of provisional application 63/202,173, filed on May 28, 2021.
Int. Cl. G06F 9/455 (2018.01); G06F 30/398 (2020.01); G06F 117/04 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2117/04 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
accessing data that describes a clock network of a circuit design, the clock network comprising a set of clock gates controlled by a corresponding set of enable conditions, the set of clock gates controlling clock signals to a set of clocked circuit elements of the circuit design;
generating a set of clock gate labels for the set of clock gates by, for each individual clock gate in the set of clock gates:
assigning a clock gate label to the individual clock gate; and
associating the clock gate label with an individual enable condition, from the corresponding set of enable conditions, for the individual clock gate;
for each individual clocked circuit element in the set of clocked circuit elements, assigning a select label from the set of clock gate labels to the individual clocked circuit element, the select label corresponding to a select clock gate that controls a clock signal to the individual clocked circuit element;
assigning an ungated label to all other clocked circuit elements that are not controlled by any clock gates; and
removing redundant logic from the circuit design by performing a depth-first search of the circuit design starting from each clocked circuit element of the circuit design.