CPC G06F 30/392 (2020.01) [H01L 27/0886 (2013.01); H01L 29/7831 (2013.01)] | 20 Claims |
1. An integrated chip comprising:
a continuous fin arranged over a substrate;
a first gate electrode extending over the continuous fin;
a first gate dielectric layer arranged between the first gate electrode and the continuous fin and having a first thickness;
a second gate electrode extending over the continuous fin;
a second gate dielectric layer arranged between the second gate electrode and the continuous fin and having a second thickness;
a dummy gate electrode extending over the continuous fin and arranged between the first gate electrode and the second gate electrode; and
a dummy gate dielectric layer arranged between the dummy gate electrode and the continuous fin and having a third thickness,
wherein the third thickness is greater than the first thickness and is greater than the second thickness.
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