US 11,797,743 B2
Leakage reduction between two transistor devices on a same continuous fin
Chun-Yen Lin, Hsinchu (TW); Bao-Ru Young, Zhubei (TW); and Tung-Heng Hsieh, Zhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 25, 2020, as Appl. No. 17/104,730.
Application 17/104,730 is a continuation of application No. 16/798,660, filed on Feb. 24, 2020, granted, now 10,867,101.
Prior Publication US 2021/0264090 A1, Aug. 26, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01)
CPC G06F 30/392 (2020.01) [H01L 27/0886 (2013.01); H01L 29/7831 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a continuous fin arranged over a substrate;
a first gate electrode extending over the continuous fin;
a first gate dielectric layer arranged between the first gate electrode and the continuous fin and having a first thickness;
a second gate electrode extending over the continuous fin;
a second gate dielectric layer arranged between the second gate electrode and the continuous fin and having a second thickness;
a dummy gate electrode extending over the continuous fin and arranged between the first gate electrode and the second gate electrode; and
a dummy gate dielectric layer arranged between the dummy gate electrode and the continuous fin and having a third thickness,
wherein the third thickness is greater than the first thickness and is greater than the second thickness.