US 11,797,471 B2
System and method for controlling a computer to receive external data for out-of-band management
Tai-Seng Lam, Taipei (TW); Li-Chun Chou, Taipei (TW); Shui-Chin Tsai, Taipei (TW); and Ting-You Liou, Taipei (TW)
Assigned to FLYTECH TECHNOLOGY CO., LTD., Taipei (TW)
Filed by FLYTECH TECHNOLOGY CO., LTD., Taipei (TW)
Filed on Jun. 17, 2022, as Appl. No. 17/842,973.
Claims priority of application No. 111102739 (TW), filed on Jan. 22, 2022.
Prior Publication US 2023/0237004 A1, Jul. 27, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 8/65 (2018.01); G06F 13/16 (2006.01); G06F 13/38 (2006.01)
CPC G06F 13/4291 (2013.01) [G06F 8/65 (2013.01); G06F 13/1668 (2013.01); G06F 13/382 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A system for controlling a computer to receive external data for out-of-band (COB) management, the computer including a host connector, said system comprising:
a switch unit configured to be electrically connected to the host connector;
an embedded controller (EC) electrically connected to said switch unit; and
a management device including a device connector that is configured to be electrically connected to the host connector, and a microcontroller that is electrically connected to said device connector and that is configured to send external data via said device connector to said EC,
wherein, when said EC is supplied with electricity, said EC controls said switch unit to establish an electrical connection between said EC and the host connector so as to allow said EC to communicate with said microcontroller through said device connector and the host connector to receive the external data from said microcontroller.
 
9. A method for controlling a computer to receive external data for out-of-band (COB) management, the computer including a host connector, the method to be implemented by a system that includes an embedded controller (EC), a memory device and a management device, the management device including a microcontroller, the method comprising steps of:
the EC operating in a master mode to perform a signal detection through a serial communication bus that uses a master-slave architecture to detect whether a slave device that supports a predefined protocol is connected to the serial communication bus;
the microcontroller operating in a slave mode, and establishing communication with the EC and adjusting voltage levels respectively on a serial data line (SDA) and a serial clock line (SCL) of the serial communication bus in response to receipt of the detection signal in a manner that the voltage levels on the SDA and the SCL satisfy a predefined condition;
when it is determined that the voltage levels on the SDA line and the SCL line of the serial communication bus satisfy the predefined condition, the EC determining whether the computer malfunctions or needs the external data, when it is determined that the computer malfunctions or needs the external data, the EC enabling the microcontroller to switch to the master mode by adjusting the voltage levels on the SDA line and the SCL line to satisfy the predefined condition for a preset mode-switching time period, and switching to the slave mode;
the microcontroller operating in the master mode to transmit external data via the serial communication bus to the EC;
after transmission of the external data is completed, the microcontroller notifying the EC of the completion of the transmission;
in response to receipt of the notification of the completion of the transmission, the EC switching to the master mode and adjusting the voltage levels on the SDA and the SCL of the serial communication bus in a manner that the voltage levels on the SDA and the SCL satisfy the predefined condition so as to enable the microcontroller to switch to the slave mode; and
after receiving the external data, the EC storing the external data in the memory device and executing a related procedure based on the external data.