US 11,797,458 B2
Terminal management device and terminal device
Hiroaki Takano, Saitama (JP); Naoyuki Sato, Tokyo (JP); Katsuyoshi Kanemoto, Chiba (JP); Erika Saito, Tokyo (JP); Hirotaka Suzuki, Kanagawa (JP); and Taichi Yuki, Kanagawa (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Appl. No. 16/477,340
Filed by SONY CORPORATION, Tokyo (JP)
PCT Filed Oct. 25, 2018, PCT No. PCT/JP2018/039739
§ 371(c)(1), (2) Date Jul. 11, 2019,
PCT Pub. No. WO2019/123832, PCT Pub. Date Jun. 27, 2019.
Claims priority of application No. 2017-242316 (JP), filed on Dec. 19, 2017.
Prior Publication US 2019/0377695 A1, Dec. 12, 2019
Int. Cl. G06F 13/00 (2006.01); H04L 67/12 (2022.01); H04W 4/50 (2018.01); H04W 4/70 (2018.01)
CPC G06F 13/00 (2013.01) [H04L 67/12 (2013.01); H04W 4/50 (2018.02); H04W 4/70 (2018.02)] 18 Claims
OG exemplary drawing
 
1. A terminal management device, comprising:
a receiving unit configured to receive, from a terminal that collects information from a sensor, access timing information related to an accessible timing to the terminal; and
a transmitting unit configured to transmit the access timing information to a server that searches for the information,
wherein the access timing information differs in frequency and time of the accessible timing to the terminal in accordance with a difference in a platform and a priority of the terminal,
wherein the access timing information is defined so that a frequency of the accessible timing to the terminal is a first frequency based on the priority of the terminal being a first priority and the frequency of the accessible timing to the terminal is a second frequency higher than the first frequency based on the priority of the terminal being a second priority higher than the first priority,
wherein the accessible timing to the terminal occurs a first number of times within a period of time in the first frequency and the accessible timing to the terminal occurs a second number of times within the period of time in the second frequency, the second number of times being higher than the first number of times, and
wherein the receiving unit and the transmitting unit are each implemented via at least one processor.