CPC G06F 12/1491 (2013.01) [G06F 12/1408 (2013.01); G06F 12/1425 (2013.01); G06F 12/1466 (2013.01)] | 8 Claims |
1. An electronic apparatus comprising:
a first memory configured to store information by a plurality of banks;
a second memory configured to store state information indicating whether or not update on the information of the first memory is allowed;
a gate device provided on a bus and configured to control whether or not to permit access to the second memory based on a control instruction; and
one or more hardware processors configured to
output, to the gate device, a control instruction to permit access to the second memory corresponding to a predetermined mode,
set the state information of the second memory to indicate an updatable state, and
update the information of the first memory,
wherein the one or more hardware processors are configured to
perform the update of the information based on presence or absence of monotonicity between the information in the first memory and the update information, and
perform the update of the information based on monotonicity between banks storing pieces of information to be updated.
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