US 11,796,879 B2
Array substrate, display panel and display device
Jiao Gao, Xiamen (CN); Yingzhang Qiu, Xiamen (CN); Limin Lin, Xiamen (CN); Xiaoli Liu, Xiamen (CN); and Yongjin Teng, Xiamen (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Appl. No. 17/416,511
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
PCT Filed Jun. 22, 2020, PCT No. PCT/CN2020/097321
§ 371(c)(1), (2) Date Jun. 20, 2021,
PCT Pub. No. WO2021/217830, PCT Pub. Date Nov. 4, 2021.
Claims priority of application No. 202010366733.2 (CN), filed on Apr. 30, 2020.
Prior Publication US 2022/0334422 A1, Oct. 20, 2022
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1368 (2013.01) [G02F 1/136209 (2013.01); G02F 1/136227 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base substrate;
a thin-film transistor disposed on a side of the base substrate, wherein the thin-film transistor comprises at least a first electrode;
a pixel electrode disposed on a side of the thin-film transistor facing away from the base substrate; and
at least two color resist layers disposed between the thin-film transistor and the pixel electrode, wherein a medium layer is disposed between any two adjacent color resist layers of the at least two color resist layers,
wherein the pixel electrode is electrically connected to the first electrode of the thin-film transistor through a via, and the via penetrates through the at least two color resist layers and the medium layer disposed between the any two adjacent color resist layers,
wherein the array substrate further comprises a planarization layer disposed between the pixel electrode and the thin-film transistor, and the planarization layer is an insulating layer,
wherein the at least two color resist layers are disposed between the planarization layer and the pixel electrode; or, the at least two color resist layers are disposed between the planarization layer and the thin-film transistor; or the at least two color resist layers comprise at least one first color resist layer and at least one second color resist layer, wherein the at least one first color resist layer is disposed between the planarization layer and the pixel electrode, and the at least one second color resist layer is disposed between the planarization layer and the thin-film transistor.