US 11,795,577 B2
SiC epitaxial wafer and method of manufacturing SiC epitaxial wafer
Kensho Tanaka, Chichibu (JP); and Yoshikazu Umeta, Chichibu (JP)
Assigned to Resonac Corporation, Tokyo (JP)
Filed by SHOWA DENKO K. K., Tokyo (JP)
Filed on Aug. 2, 2022, as Appl. No. 17/879,474.
Claims priority of application No. 2021-128273 (JP), filed on Aug. 4, 2021.
Prior Publication US 2023/0038132 A1, Feb. 9, 2023
Int. Cl. C30B 29/36 (2006.01); H01L 29/16 (2006.01); H01L 29/167 (2006.01); H01L 21/02 (2006.01); C23C 16/44 (2006.01); C30B 25/20 (2006.01); C30B 25/16 (2006.01); C23C 16/32 (2006.01); C23C 16/52 (2006.01)
CPC C30B 29/36 (2013.01) [C23C 16/325 (2013.01); C23C 16/4408 (2013.01); C23C 16/52 (2013.01); C30B 25/16 (2013.01); C30B 25/205 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A SiC epitaxial wafer, comprising:
a SiC substrate; and,
an epitaxial layer of SiC laminated on the SiC substrate,
wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and
the concentration of boron is less than 1.0×1014 cm−3 at any position in the plane of the epitaxial layer.