US 12,453,294 B2
Multi-level programming of phase change memory device
Kangguo Cheng, Schenectady, NY (US); Juntao Li, Cohoes, NY (US); Ching-Tzu Chen, Ossining, NY (US); and Carl Radens, LaGrangeville, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 9, 2021, as Appl. No. 17/547,152.
Prior Publication US 2023/0189667 A1, Jun. 15, 2023
Int. Cl. H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10N 70/011 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A phase change memory cell, comprising:
a phase change structure;
a heater coupled to a first surface of the phase change structure;
a first electrode coupled to a second surface of the phase change structure;
a second electrode coupled to a second surface of the heater;
a third electrode connected to a first lateral end of the phase change structure; and
a fourth electrode connected to a second lateral end of the phase change structure,
wherein the phase change structure comprises a stack of alternating layers of a resistive liner (RL) layer and a phase change memory (PCM) layer and a thickness of at least one PCM layer in the stack of alternating layers of the RL layer and the PCM layer is different from thicknesses of other PCM layers in the stack of alternating layers.