US 12,453,290 B2
Memory cell, memory device and manufacturing method thereof
Kai-Tai Chang, Kaohsiung (TW); Chien-Min Lee, Hsinchu County (TW); Tung-Ying Lee, Hsinchu (TW); and Shy-Jay Lin, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 16, 2022, as Appl. No. 17/744,732.
Prior Publication US 2023/0371400 A1, Nov. 16, 2023
Int. Cl. H10N 52/01 (2023.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 52/80 (2023.01)
CPC H10N 50/10 (2023.02) [H10B 61/00 (2023.02); H10B 61/10 (2023.02); H10B 61/22 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a spin Hall electrode layer;
a magnetic tunneling junction (MTJ) pillar disposed on the spin Hall electrode layer;
a hard mask disposed on the MTJ pillar; and
a spacer disposed on sidewalls of the MTJ pillar and the hard mask, wherein the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion,
wherein a bottom edge of an outer sidewall of the spacer and a sidewall of the inner portion of the spin Hall electrode layer are substantially vertically aligned with each other.