US 12,453,246 B2
Display panel and display apparatus
Jieliang Li, Xiamen (CN); and Jiaxian Liu, Xiamen (CN)
Assigned to XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Jan. 2, 2024, as Appl. No. 18/401,975.
Application 18/401,975 is a continuation of application No. 18/150,953, filed on Jan. 6, 2023, granted, now 11,903,257.
Application 18/150,953 is a continuation of application No. 17/147,309, filed on Jan. 12, 2021, granted, now 11,574,978, issued on Feb. 7, 2023.
Claims priority of application No. 202011150331.5 (CN), filed on Oct. 23, 2020.
Prior Publication US 2024/0138191 A1, Apr. 25, 2024
Prior Publication US 2024/0237408 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 59/121 (2023.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10K 59/1216 (2023.02) [G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); H10K 59/1213 (2023.02); G09G 2320/0626 (2013.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a driving array layer, wherein the driving array layer comprises a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit;
wherein the pixel circuit comprises a first transistor and a first capacitor, and the driving circuit comprises a second transistor and a second capacitor, wherein the first transistor comprises a first active layer comprising silicon, and the second transistor comprises a second active layer comprising oxide semiconductor;
wherein in a direction perpendicular to a plane of the display panel, the first capacitor partially overlaps the first transistor, and the second capacitor does not overlap the second transistor, or
in a direction perpendicular to a plane of the display panel, an area of a region where the first capacitor overlaps the first transistor is greater than an area of a region where the second capacitor overlaps the second transistor; and
wherein the display panel further comprises:
a base substrate, wherein the driving array layer is disposed on the base substrate and comprises a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer that are sequentially arranged in a direction facing away from the base substrate;
wherein the first transistor further comprises a first gate electrode, a first source electrode, and a first drain electrode;
wherein the second transistor further comprises a second gate electrode, a third gate electrode, a second source electrode, and a second drain electrode; and
wherein the first gate electrode is located in the first metal layer, the second gate electrode is located in the second metal layer, the third gate electrode is located in the third metal layer, and at least one of the first source electrode, the first drain electrode, the second source electrode, or the second drain electrode is located in the fourth metal layer.