US 12,453,241 B2
Display device and method for manufacturing display device
Tamotsu Sakai, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 18/034,343
Filed by SHARP KABUSHIKI KAISHA, Sakai (JP)
PCT Filed Oct. 30, 2020, PCT No. PCT/JP2020/040839
§ 371(c)(1), (2) Date Apr. 27, 2023,
PCT Pub. No. WO2022/091348, PCT Pub. Date May 5, 2022.
Prior Publication US 2024/0306425 A1, Sep. 12, 2024
Int. Cl. H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10K 59/1201 (2023.02) [H10K 59/1213 (2023.02); H10D 86/421 (2025.01); H10D 86/60 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A display device comprising:
a light-emitting element; and
a pixel circuit including a transistor including a first structure,
wherein a semiconductor layer of the transistor including the first structure includes a first channel region, a first doped region adjacent to one side of the first channel region, and a second doped region adjacent to another side of the first channel region,
the first doped region is constituted by a high concentration region doped with an impurity at a high concentration,
the second doped region is constituted by a low concentration region adjacent to the first channel region, the low concentration region being doped with an impurity at a low concentration, and a high concentration region adjacent to the low concentration region, the high concentration region being doped with an impurity at a high concentration,
the pixel circuit includes a drive transistor serving as the transistor including the first structure and a capacitance element connected to a gate electrode of the drive transistor,
a drive current flows from the first doped region to the second doped region of the drive transistor in a light emission period of the light-emitting element,
the pixel circuit includes a transistor including a second structure,
a semiconductor layer of the transistor including the second structure includes a second channel region, a third doped region adjacent to one side of the second channel region, and a fourth doped region adjacent to another side of the second channel region,
the third doped region includes a low concentration region adjacent to the second channel region, the low concentration region being doped with an impurity at a low concentration, and a high concentration region adjacent to the low concentration region, the high concentration region being doped with an impurity at a high concentration,
the fourth doped region includes a low concentration region adjacent to the second channel region, the low concentration region being doped with an impurity at a low concentration, and a high concentration region adjacent to the low concentration region, the high concentration region being doped with an impurity at a high concentration, and
the pixel circuit includes a threshold control transistor serving as the transistor including the second structure, the threshold control transistor being connected to a scanning signal line of a current stage and a gate electrode of the drive transistor.