	US 12,453,204 B2
	Semiconductor package and method of manufacturing the same
Jaegwon Jang, Hwaseong-si (KR); Seokhyun Lee, Hwaseong-si (KR); and Kyoung Lim Suk, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 23, 2020, as Appl. No. 17/101,642.
Application 17/101,642 is a continuation of application No. 16/364,237, filed on Mar. 26, 2019, granted, now 10,879,292.
Claims priority of application No. 10-2018-0110044 (KR), filed on Sep. 14, 2018.
Prior Publication US 2021/0074754 A1, Mar. 11, 2021
Int. Cl. H10F 39/00 (2025.01); H01L 23/31 (2006.01); H01L 23/485 (2006.01); H01L 25/065 (2023.01); H10F 39/12 (2025.01)

CPC H10F 39/809 (2025.01) [H01L 23/3157 (2013.01); H01L 23/485 (2013.01); H01L 25/0657 (2013.01); H10F 39/026 (2025.01); H10F 39/804 (2025.01); H10F 39/811 (2025.01); H10F 39/199 (2025.01)]

17 Claims

1. A semiconductor package, comprising:

a first redistribution layer;

a first semiconductor chip on the first redistribution layer, the first semiconductor chip having a bottom surface facing the first redistribution layer and a top surface opposite to the bottom surface;

a first molding layer on the first redistribution layer and covering the first semiconductor chip;

a plurality of metal pillars around the first semiconductor chip and connected to the first redistribution layer, the metal pillars extending axially through the first molding layer;

a second redistribution layer on the first molding layer and connected to the metal pillars;

a second semiconductor chip on the second redistribution layer, the second semiconductor chip having conductive pads at a top surface thereof;

a third semiconductor chip on a side of the first redistribution layer opposite that on which the first semiconductor chip is disposed such that the first redistribution layer is interposed between the first semiconductor chip and the third semiconductor chip; and

a second molding layer on the first redistribution layer and covering a side of the third semiconductor chip,

wherein a lateral surface of the first redistribution layer is coplanar with a lateral surface of the first molding layer, a lateral surface of the second redistribution layer, and a lateral surface of the second semiconductor chip,

wherein a top surface of the second molding layer is coplanar with a top surface of the third semiconductor chip,

wherein the first semiconductor chip includes a plurality of chip pads on the bottom surface thereof, and

wherein the first molding layer includes a first portion between the bottom surface of the first semiconductor chip and the first redistribution layer and a second portion between the top surface of first semiconductor chip and the second redistribution layer.

10. A semiconductor package, comprising:

a first redistribution layer;

a first semiconductor chip on the first redistribution layer, the first semiconductor chip having a bottom surface facing a first side of the first redistribution layer and a top surface opposite to the bottom surface;

a first molding layer on the first redistribution layer and covering the first semiconductor chip;

a plurality of metal pillars around the first semiconductor chip and connected to the first redistribution layer, the metal pillars extending axially through the first molding layer;

a second redistribution layer on the first molding layer, the second redistribution layer comprising a plurality of connection pads connected to the metal pillars;

a second semiconductor chip on the second redistribution layer, the second semiconductor chip comprising a plurality of chip pads coupled to the connection pads;

a third semiconductor chip on a second side of the first redistribution layer opposite to the first side of the first redistribution layer; and

a second molding layer on the second side of the first redistribution layer and covering a lateral surface of the third semiconductor chip,

wherein a side surface of the second semiconductor chip is coplanar with a lateral surface of the first molding layer, and

wherein the chip pads of the second semiconductor chip directly contact with the connection pads of the second redistribution layer, respectively,

wherein the first semiconductor chip includes a plurality of chip pads on the bottom surface thereof,

wherein a top surface of the second molding layer is coplanar with a top surface of the third semiconductor chip,

15. A semiconductor package, comprising:

a first chip;

a second chip on the first chip;

a third chip on the second chip;

a first redistribution layer interposed between the first chip and the third chip;

a second redistribution layer interposed between the first chip and the second chip;

a first molding layer interposed between the first redistribution layer and the second redistribution layer;

a second molding layer covering a lateral surface of the third chip; and

a plurality of metal pillars penetrating the first molding layer and connecting the first redistribution layer with the second redistribution layer,

wherein a lateral surface of the first molding layer is coplanar with lateral surfaces of the first and second redistribution layers,

wherein a lateral surface of the second molding layer is coplanar with the lateral surface of the first molding layer,

wherein a top surface of the second molding layer is coplanar with a top surface of the third chip,

wherein the first chip has a bottom surface facing the first redistribution layer and a top surface opposite to the bottom surface, and

wherein the first molding layer includes a first portion between the bottom surface of the first chip and the first redistribution layer and a second portion between the top surface of first chip and the second redistribution layer.