| CPC H10F 39/807 (2025.01) [H01L 21/76224 (2013.01); H10F 39/199 (2025.01); H10F 39/8067 (2025.01); H01L 21/3065 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32051 (2013.01); H10F 39/18 (2025.01); H10F 39/8053 (2025.01); H10F 39/8063 (2025.01)] | 20 Claims |

|
1. A structure comprising:
a semiconductor substrate;
a Deep Trench Isolation (DTI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the DTI region comprises:
a dielectric layer comprising:
a first portion in the semiconductor substrate; and
a second portion higher than the semiconductor substrate, wherein the second portion of the dielectric layer overlaps the semiconductor substrate;
a diffusion barrier layer over the dielectric layer; and
a high-reflectivity metal layer between opposite portions of the dielectric layer, wherein the high-reflectivity metal layer encloses a void therein, and wherein the diffusion barrier layer is between the dielectric layer and the high-reflectivity metal layer;
pixel units with portions in the semiconductor substrate;
color filters overlapping the pixel units; and
micro lenses overlapping the color filters.
|