US 12,453,185 B2
Protection of a domain of an integrated circuit against overvoltages
Nicolas Moeneclaey, Vourey (FR); and Jean-Luc Patry, Crolles (FR)
Assigned to STMicroelectronics (Alps) SAS, Grenoble (FR); and STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Alps) SAS, Grenoble (FR)
Filed on Oct. 20, 2022, as Appl. No. 17/969,867.
Claims priority of application No. 2112211 (FR), filed on Nov. 18, 2021.
Prior Publication US 2023/0154919 A1, May 18, 2023
Int. Cl. H10D 89/60 (2025.01)
CPC H10D 89/611 (2025.01) [H10D 89/713 (2025.01); H10D 89/911 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
an input/output cell comprising:
a first signal terminal for receiving/transmitting a signal,
a third signal terminal coupled to a domain and configured to operate under a power supply voltage and capable of withstanding a maximum voltage greater than the power supply voltage, and
an array comprising N diodes coupled in series between the third signal terminal and a cold power supply point, N being an integer greater than 0, the array having an overall threshold voltage greater than the maximum voltage; and
a control circuit coupled between the first signal terminal and the array, the control circuit configured to, in a presence of a second voltage on the first signal terminal greater than the maximum voltage, automatically and autonomously short-circuit at least one diode in the array to limit a voltage on the third signal terminal to a third voltage less than the maximum voltage, the control circuit comprising:
a second resistor coupled between the first signal terminal and the third signal terminal,
a first transistor, a drain terminal of the first transistor coupled to a node of the array located between two consecutive diodes, a source terminal of the first transistor coupled to the cold power supply point,
a second transistor, a source terminal of the second transistor coupled to the second resistor, a gate terminal of the second transistor coupled to the third signal terminal, and a drain terminal of the second transistor coupled to the gate terminal of the first transistor.