| CPC H10D 89/10 (2025.01) [H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H10D 84/05 (2025.01); H10D 84/403 (2025.01)] | 12 Claims |

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1. A microelectronic device, comprising:
a substrate;
at least two doped well regions being disposed in said substrate and being spaced apart from each other by said substrate, each of said at least two doped well regions having a doping type opposite to that of said substrate;
an epitaxial structure disposed on said substrate, and being in contact with said at least two doped well regions, said epitaxial structure including a channel layer that has a first portion and a second portion respectively located above said at least two doped well regions;
at least two power elements respectively disposed on said first and second portion of said epitaxial structure opposite to said substrate and being cascade connected with each other, each of said at least two power elements having a high potential terminal and a low potential terminal;
at least two conductive vias that are spaced apart from each other, and that penetrate through said epitaxial structure to respectively contact said at least two doped well regions, said low potential terminal of each of said at least two power elements being electrically connected to the respective one of said at least two doped well regions through a respective one of said conductive vias; and
an isolation structure formed in said epitaxial structure between said first portion and said second portion to isolate said at least two power elements,
wherein each of said at least two power elements is disposed on one of said first and second portions above a respective one of said at least two doped well regions;
wherein each of said power elements includes a source, a drain, and a gate, said drain being said high potential terminal, said source being said low potential terminal, said source of one of said power elements being cascade connected to said drain of the other one of said power elements, said isolation structure being spacedly located above said substrate and being adjacent to one of said conductive vias disposed between said source of said one of said power elements and said drain of said other one of said power elements, which are cascade connected to each other.
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