| CPC H10D 86/423 (2025.01) [H10D 30/6733 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a third wiring, and a fourth wiring,
wherein the first transistor comprises a first semiconductor layer, and a first gate and a second gate that overlap with each other with the first semiconductor layer therebetween,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the one of the source and the drain of the first transistor is directly connected to the second gate, and wherein the other of the source and the drain of the first transistor is directly connected to one of a source and a drain of the second transistor and one electrode of the capacitor, wherein the second transistor comprises a second semiconductor layer and a third gate,
wherein the third gate of the second transistor is electrically connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring, wherein a first potential is supplied to the one of the source and the drain of the first transistor from the first wiring,
wherein a second potential and a third potential are alternately supplied to the other of the source and the drain of the second transistor directly from the second wiring,
wherein the first potential is lower than the second potential,
wherein the third potential is lower than the second potential,
wherein the third wiring is electrically connected to the first gate,
a first signal is supplied to the first gate from the third wiring, and wherein the fourth wiring is electrically connected to the third gate, and
wherein a second signal obtained by inverting the first signal is supplied to the third gate from the fourth wiring.
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