| CPC H10D 86/201 (2025.01) [H10D 1/047 (2025.01); H10D 1/66 (2025.01); H10D 86/01 (2025.01)] | 20 Claims |
|
1. An integrated circuit (IC) structure, comprising:
a semiconductor-on-insulator (SOI) substrate, including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer; and
a gate over a gate dielectric layer over the SOI layer;
an n-type metal-oxide semiconductor (n-MOS) capacitor, including:
an n-well under the buried insulator layer, and
an n-type semiconductor adjacent a first side of the gate; and
a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and including:
a p-well adjacent the n-well, and
a p-type semiconductor adjacent a second side of the gate, and
wherein the gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.
|