US 12,453,177 B2
Integrated circuit including asymmetric ending cells and system-on-chip including the same
Jong-kyu Ryu, Seoul (KR); Min-su Kim, Hwaseong-si (KR); and Dae-seong Lee, Busan (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 1, 2021, as Appl. No. 17/515,747.
Application 16/876,694 is a division of application No. 15/963,629, filed on Apr. 26, 2018, granted, now 10,680,014, issued on Jun. 9, 2020.
Application 17/515,747 is a continuation of application No. 16/876,694, filed on May 18, 2020, granted, now 11,189,640.
Claims priority of application No. 10-2017-0114698 (KR), filed on Sep. 7, 2017.
Prior Publication US 2022/0059572 A1, Feb. 24, 2022
Int. Cl. H10D 84/90 (2025.01); H01L 23/528 (2006.01); H10D 1/68 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01); H10D 1/66 (2025.01)
CPC H10D 84/907 (2025.01) [H01L 23/5286 (2013.01); H10D 1/692 (2025.01); H10D 84/853 (2025.01); H10D 84/854 (2025.01); H10D 89/10 (2025.01); H10D 1/66 (2025.01); H10D 84/942 (2025.01); H10D 84/961 (2025.01); H10D 84/971 (2025.01); H10D 84/975 (2025.01); H10D 84/981 (2025.01); H10D 84/991 (2025.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of standard cells in a first area;
a first plurality of dummy cells placed along portions of a boundary extending in a first direction around the plurality of standard cells, the first plurality of dummy cells abutting one another;
a second plurality of dummy cells placed along a first portion of the boundary extending in a second direction around the plurality of standard cells, the second plurality of dummy cells abutting one another, each of the second plurality of dummy cells having a first width in the first direction;
a third plurality of dummy cells placed along a second portion of the boundary extending in the second direction around the plurality of standard cells, the third plurality of dummy cells abutting one another, the third plurality of dummy cells being opposite to the second plurality of dummy cells with the plurality of standard cells therebetween, each of the third plurality of dummy cells having a second width in the first direction;
one or more dummy cells placed along one or more remaining portions of the boundary not covered by the first plurality of dummy cells, the second plurality of dummy cells, and the third plurality of dummy cells to form a ring of dummy cells around the plurality of standard cells,
a first macroblock adjacent to the second plurality of dummy cells; and
a second macroblock adjacent to the third plurality of dummy cells,
wherein the first plurality of dummy cells and the second plurality of dummy cells are placed at a distance inside the first area,
wherein the first width is different from the second width,
wherein each of the second plurality of dummy cells includes a tap configured to receive a power supply voltage or a ground voltage and provide the power supply voltage or the ground voltage to a first active region, and
wherein each of the third plurality of dummy cells includes no tap such that the second width is less than the first width.