| CPC H10D 84/834 (2025.01) [H01L 21/3086 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 12 Claims |
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1. A semiconductor device, comprising:
first active fins that protrude from a substrate;
second active fins that protrude from the substrate and are spaced apart from the first active fins;
a device isolation pattern between the first active fins and the second active fins, the device isolation pattern including a recess in a portion of an upper surface of the device isolation pattern;
a first gate pattern that crosses over the first active fins;
a second gate pattern that crosses over the second active fins; and
a separation pattern between the first gate pattern and the second gate pattern,
wherein the first gate pattern includes a first high-k dielectric pattern, a first work function pattern on the first high-k dielectric pattern, a first metal line pattern on the first work function pattern, and a first gate capping pattern on the first metal line pattern,
wherein a sidewall of the first work function pattern is aligned with a lower sidewall of the first high-k dielectric pattern,
wherein the first metal line pattern is in contact with the sidewall of the first work function pattern,
wherein the separation pattern extends into the recess to contact a bottom surface of the recess and is spaced apart from the first work function pattern, and
wherein a sidewall of the separation pattern is in contact with the device isolation pattern, the first metal line pattern, and the first gate capping pattern.
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