US 12,453,170 B2
Integration of nanosheets with bottom dielectric isolation and ideal diode
Andrew Gaul, Halfmoon, NY (US); Anthony I. Chou, Guilderland, NY (US); Julien Frougier, Albany, NY (US); and Andrew M. Greene, Slingerlands, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,827.
Prior Publication US 2024/0072041 A1, Feb. 29, 2024
Int. Cl. H01L 27/06 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/861 (2006.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/80 (2025.01)
CPC H10D 84/811 (2025.01) [H01L 21/02603 (2013.01); H01L 21/26513 (2013.01); H10D 8/041 (2025.01); H10D 8/825 (2025.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a diode in a first region of a bulk substrate, wherein the diode comprises P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed directly on a top layer of the P-N-P vertical implanted layers; and
a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate.