US 12,453,161 B2
Semiconductor device with air-spacer
Wei-Yang Lee, Taipei (TW); Feng-Cheng Yang, Hsinchu County (TW); Chung-Te Lin, Tainan (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/446,190.
Application 18/446,190 is a continuation of application No. 17/322,595, filed on May 17, 2021, granted, now 11,830,922.
Application 17/322,595 is a continuation of application No. 16/721,335, filed on Dec. 19, 2019, granted, now 11,201,228, issued on Dec. 14, 2021.
Application 16/721,335 is a continuation of application No. 15/623,539, filed on Jun. 15, 2017, granted, now 10,522,642, issued on Dec. 31, 2019.
Claims priority of provisional application 62/434,336, filed on Dec. 14, 2016.
Prior Publication US 2023/0387247 A1, Nov. 30, 2023
Int. Cl. H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/302 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 30/69 (2025.01); H10D 62/822 (2025.01)
CPC H10D 64/679 (2025.01) [H01L 21/02068 (2013.01); H01L 21/302 (2013.01); H01L 21/311 (2013.01); H10D 30/0225 (2025.01); H10D 62/115 (2025.01); H10D 64/015 (2025.01); H10D 64/256 (2025.01); H10D 64/671 (2025.01); H10D 30/797 (2025.01); H10D 62/822 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
two source/drain (S/D) regions over a substrate;
a gate stack over the substrate and between the two S/D regions, the gate stack having a gate dielectric layer and a gate electrode layer over the gate dielectric layer;
a spacer layer covering sidewalls of the gate stack;
an S/D contact metal over one of the two S/D regions;
a first dielectric layer covering sidewalls of the S/D contact metal and an upper surface of the two S/D regions; and
a second dielectric layer covering the first dielectric layer, the spacer layer, and the gate stack, and defining an air gap, wherein an extent of a first sidewall of the air gap from a bottommost point to an uppermost point is a sidewall of the first dielectric layer, a second sidewall of the air gap is a sidewall of the spacer layer, a top surface of the air gap defines the uppermost point and is a bottom surface of the second dielectric layer, wherein a material of the first sidewall of the air gap is different from material of the top surface of the air gap, and a material of the second sidewall of the air gap is different from the material of the top surface of the air gap, wherein a top surface of the first dielectric layer and a top surface of the gate electrode layer are coplanar, and a top surface of the S/D contact metal is above the top surface of the gate electrode layer and the top surface of the first dielectric layer.