US 12,453,159 B2
Drain side recess for back-side power rail device
Huan-Chieh Su, Tianzhong Township (TW); Cheng-Chi Chuang, New Taipei (TW); Chih-Hao Wang, Baoshan Township (TW); and Kuo-Cheng Chiang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/883,677.
Application 17/883,677 is a division of application No. 17/123,873, filed on Dec. 16, 2020, granted, now 11,658,220.
Claims priority of provisional application 63/014,880, filed on Apr. 24, 2020.
Prior Publication US 2022/0384589 A1, Dec. 1, 2022
Int. Cl. H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 64/254 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/251 (2025.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor transistor device, comprising:
forming a stack of semiconductor layers as a channel structure;
forming a gate structure wrapping around the channel structure;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the channel structure;
etching a bottom of the second source/drain epitaxial structure to form a concave bottom surface;
forming a first dielectric liner overlying the second source/drain epitaxial structure; and
forming a source/drain contact along a sidewall of the first dielectric liner and contacting a bottom of the second source/drain epitaxial structure.