US 12,453,157 B2
MOS device with resistive field plate for realizing conductance modulation field effect and preparation method thereof
Kaizhou Tan, Chongqing (CN); Tian Xiao, Chongqing (CN); Jiahao Zhang, Chongqing (CN); Yonghui Yang, Chongqing (CN); Xiaoquan Li, Chongqing (CN); Pengfei Wang, Chongqing (CN); Ying Pei, Chongqing (CN); Guangbo Li, Chongqing (CN); Hequan Jiang, Chongqing (CN); Peijian Zhang, Chongqing (CN); Sheng Qiu, Chongqing (CN); Liang Chen, Chongqing (CN); and Wei Cui, Chongqing (CN)
Assigned to NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing (CN)
Appl. No. 17/925,322
Filed by NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing (CN)
PCT Filed Apr. 26, 2021, PCT No. PCT/CN2021/089923
§ 371(c)(1), (2) Date Nov. 15, 2022,
PCT Pub. No. WO2022/095347, PCT Pub. Date May 12, 2022.
Claims priority of application No. 202011232183.1 (CN), filed on Nov. 6, 2020.
Prior Publication US 2024/0038853 A1, Feb. 1, 2024
Int. Cl. H10D 64/00 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01)
CPC H10D 64/115 (2025.01) [H10D 30/0297 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 62/102 (2025.01); H10D 64/117 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A MOS device with resistive field plate for realizing conductance modulation field effect, comprising:
a substrate, configured as a drain region of the MOS device;
an epitaxial layer, arranged on the substrate;
at least two MOS source regions, arranged in the epitaxial layer and at the top of the epitaxial layer;
a MOS channel region, arranged in the epitaxial layer and under the MOS source regions;
at least two trench gate structures, arranged on the top of the epitaxial layer, wherein the trench gate structures vertically cover the MOS source regions and the MOS channel region; and
at least two semi-insulating resistive field plate structures, arranged in the epitaxial layer and electrically connected with the substrate, and each located under a respective one of the trench gate structures and electrically connected with the respective trench gate structure; and
a MOS channel contact region, arranged at the top part of the epitaxial layer, between two of the MOS source regions and between two of the trench gate structures, and connected with the MOS channel region;
wherein at least two trenches are formed in the epitaxial layer, and the trenches vertically penetrate from the MOS source regions, the MOS channel region, and the epitaxial layer to the substrate; and one of the semi-insulating resistive field plate structures and one of the trench gate structures are sequentially arranged in and fill each of the trenches along a bottom-to-top direction of the respective trench;
along a sidewall of each of the trenches inward, the respective semi-insulating resistive field plate structure comprises a field plate dielectric layer and a semi-insulating resistive field plate layer; along the sidewall of each of the trenches inward, the respective trench gate structure comprises a gate dielectric layer, a first trench gate layer and a second trench gate layer; wherein the second trench gate layer is electrically connected and in direct contact with the respective semi-insulating resistive field plate layer; and the respective semi-insulating resistive field plate layer is electrically connected and in direct contact with the substrate at the bottom of the trench.