| CPC H10D 64/021 (2025.01) [H01L 21/31144 (2013.01); H01L 21/3115 (2013.01); H01L 21/32055 (2013.01); H10D 64/017 (2025.01); H10D 64/671 (2025.01); H10D 84/853 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
a source epitaxial structure and a drain epitaxial structure on opposite sides of the gate structure, respectively;
a gate spacer on a sidewall of the gate structure, the gate spacer comprising an outer spacer and a silicon nitride inner spacer between the gate structure and the outer spacer, wherein the outer spacer and the silicon nitride inner spacer have a same fluorine-containing impurity, and a concentration of the fluorine-containing impurity in the silicon nitride inner spacer is higher than a concentration of the fluorine-containing impurity in the outer spacer, a concentration of the fluorine-containing impurity within the silicon nitride inner spacer decreases from an inner sidewall of the silicon nitride inner spacer to an outer sidewall of the silicon nitride inner spacer;
an interfacial layer vertically between the gate structure and the substrate, the interfacial layer having an impurity same as the fluorine-containing impurity in the outer spacer and the silicon nitride inner spacer; and
an etch stop layer over the source epitaxial structure and the drain epitaxial structure, an upper portion of the etch stop layer having an impurity same as the impurity in the interfacial layer.
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