| CPC H10D 64/01 (2025.01) [H01L 21/28088 (2013.01); H10D 30/031 (2025.01); H10D 30/6739 (2025.01); H10D 64/017 (2025.01); H10D 84/83 (2025.01); H10D 30/6757 (2025.01)] | 20 Claims |
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1. A method comprising:
forming a dummy gate stack over a semiconductor region;
forming a source/drain region on a side of the dummy gate stack;
removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench;
forming a gate dielectric layer extending into the trench;
depositing a work-function tuning layer on the gate dielectric layer, wherein the work-function tuning layer comprises aluminum and carbon, and the depositing the work-function tuning layer comprises thermal soaking processes using a first process gas comprising aluminum, and a second process gas comprising carbon;
depositing a p-type work-function layer over the work-function tuning layer; and
performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.
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