US 12,453,151 B2
Parasitic channel mitigation in semiconductor structures
Kevin J. Linthicum, Cary, NC (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,858.
Application 18/475,858 is a continuation of application No. 17/576,316, filed on Jan. 14, 2022, granted, now 11,810,955.
Application 17/576,316 is a continuation of application No. 16/425,875, filed on May 29, 2019, granted, now 11,264,465, issued on Mar. 1, 2022.
Application 16/425,875 is a continuation of application No. 14/847,270, filed on Sep. 8, 2015, abandoned.
Prior Publication US 2024/0021678 A1, Jan. 18, 2024
Int. Cl. H10D 62/85 (2025.01); H01L 21/02 (2006.01); H10D 30/47 (2025.01); H10D 62/17 (2025.01); H10D 62/824 (2025.01)
CPC H10D 62/8503 (2025.01) [H01L 21/02381 (2013.01); H01L 21/02447 (2013.01); H01L 21/0254 (2013.01); H10D 30/47 (2025.01); H10D 62/221 (2025.01); H10D 62/824 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a III-nitride material region over a top surface of the substrate;
a first species implanted within at least one region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate; and
a second species implanted within at least one region of the III-nitride material region, wherein:
a top surface region of the substrate comprises a parasitic channel; and
the at least one region of the substrate in which the first species is implanted comprises a low-conductivity parasitic channel or is free of the parasitic channel.