| CPC H10D 62/111 (2025.01) [H10D 30/665 (2025.01); H10D 62/105 (2025.01); H10D 62/107 (2025.01)] | 13 Claims |
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1. A superjunction semiconductor device comprising:
a substrate;
an epitaxial layer on the substrate;
pillars in the epitaxial layer, the pillars comprising a plurality of first pillars in a cell region, a plurality of second pillars in a ring region, and a plurality of third pillars in a transition region;
a first body region in the epitaxial layer and electrically connected to a corresponding one of the first pillars;
a source in the first body region;
a gate on the epitaxial layer;
an interlayer insulating layer on the epitaxial layer and covering the gate;
a first contact in the cell region and passing through the interlayer insulating layer;
a second contact in the transition region and passing through the interlayer insulating layer; and
a connector connecting adjacent pillars,
wherein the connector has a first width less than half of a second width of each of the second pillars and/or the third pillars.
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