US 12,453,136 B2
Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate
Serguei Jourba, Aix en Provence (FR); Catherine Decobert, Pourrieres (FR); Feng Zhou, Fremont, CA (US); Jinho Kim, Saratoga, CA (US); Xian Liu, Sunnyvale, CA (US); and Nhan Do, Saratoga, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on May 25, 2022, as Appl. No. 17/824,812.
Claims priority of provisional application 63/317,810, filed on Mar. 8, 2022.
Prior Publication US 2023/0290864 A1, Sep. 14, 2023
Int. Cl. H10D 30/68 (2025.01); H10B 41/27 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6892 (2025.01) [H10B 41/27 (2023.02); H10D 30/024 (2025.01); H10D 30/0411 (2025.01); H10D 30/6211 (2025.01); H10D 30/68 (2025.01); H10D 62/151 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method of forming a device, comprising:
providing a substrate of silicon having first, second and third areas;
recessing an upper surface of the substrate in the first area and an upper surface of the substrate in third area, relative to an upper surface of the substrate in the second area;
removing portions of the substrate in the second area to form an upwardly extending fin of silicon having a pair of side surfaces extending up and terminating at a top surface;
forming a first source region and a first drain region in the first area, wherein the first source region and the first drain region define a first channel region of the substrate extending therebetween;
forming a second source region and a second drain region in the fin of silicon to define a second channel region of the substrate extending therebetween along the top surface and the pair of side surfaces of the fin of silicon;
forming a third source region and a third drain region in the third area, wherein the third source region and the third drain region define a third channel region of the substrate extending therebetween;
forming a floating gate disposed over and insulated from a first portion of the first channel region of the substrate using a first polysilicon deposition;
forming an erase gate disposed over and insulated from the first source region and a device gate disposed over and insulated from the third channel region of the substrate using a second polysilicon deposition different from the first polysilicon deposition; and
forming a word line gate disposed over and insulated from a second portion of the first channel region, a control gate disposed over and insulated from the floating gate, and a logic gate disposed over and insulated from the second channel region of the substrate, using a metal deposition;
wherein the removing of the portions of the substrate to form the fin of silicon is performed after the recessing
wherein after the recessing and before the removing, the method further comprising:
forming trenches extending into the substrate in the first and third areas;
forming insulation material in the first and third areas; and
planarizing an upper surface of the insulation material;
wherein the trenches are filled with the insulation material after the planarizing.