US 12,453,135 B2
Thin film transistor, shift register unit, gate driving circuit and display panel
Lizhong Wang, Beijing (CN); Guangcai Yuan, Beijing (CN); Ce Ning, Beijing (CN); Hehe Hu, Beijing (CN); Nianqi Yao, Beijing (CN); Dongfang Wang, Beijing (CN); Zhengliang Li, Beijing (CN); Liping Lei, Beijing (CN); and Chen Xu, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/292,558
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 30, 2022, PCT No. PCT/CN2022/102945
§ 371(c)(1), (2) Date Jan. 26, 2024,
PCT Pub. No. WO2024/000451, PCT Pub. Date Jan. 4, 2024.
Prior Publication US 2025/0089303 A1, Mar. 13, 2025
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01)
CPC H10D 30/6757 (2025.01) [G09G 3/20 (2013.01); G11C 19/28 (2013.01); H10D 62/151 (2025.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A thin film transistor, comprising:
a source electrode, comprising a source wire and P source units electrically connected with the source wire, wherein each of the P source units comprises M source branches, and the M source branches each extends along a first direction and are arranged at intervals in a second direction intersecting the first direction;
a drain electrode, comprising a drain wire and P drain units electrically that are connected with the drain wire and in one-to-one correspondence with the P source units, wherein each of the P drain units comprises N drain branches, and the N drain branches each extends along the first direction and are arranged at intervals in the second direction; one source unit and one corresponding drain unit constitute one source-drain unit; in each of the P source-drain units, the M source branches and the N drain branches are alternately arranged, separated from each other and insulated, and M is greater than or equal to N;
a gate electrode, insulated from the source electrode and the drain electrode; and
a semiconductor layer, electrically connected to the M source branches and the N drain branches in each of the source-drain units, wherein the semiconductor layer comprises a plurality of sub-channel regions located in each of the P source-drain units, and each of the sub-channel regions is located between one of the drain branches and one of the source branches that are adjacent to each other;
a sum of widths of the plurality of sub-channel regions of the P source-drain units in the first direction is W, and an average length of the plurality of sub-channel regions of the P source-drain units in a direction perpendicular to the first direction is L;
12≤W/L≤400, P, M and N are integers greater than or equal to 1, and P×N≥4;
the source-drain units are arranged in at least one unit row, and each unit row in the at least one unit row comprises at least one source-drain unit;
in one same unit row, a distance between adjacent source-drain units is d, W≥500 μm, d ranges from 20 μm to 300 μm.