US 12,453,133 B2
Transistor structure and method of forming the same
Chien-Hao Huang, Hsinchu (TW); Gao-Ming Wu, New Taipei (TW); Katherine H Chiang, New Taipei (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 1, 2022, as Appl. No. 17/901,843.
Prior Publication US 2024/0079497 A1, Mar. 7, 2024
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01)
CPC H10D 30/6755 (2025.01) [H10D 30/031 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A transistor structure, comprising:
a gate electrode;
a gate dielectric layer, disposed on the gate electrode;
an active layer, disposed on the gate dielectric layer;
a pair of source/drain (S/D) features, disposed on the active layer; and
an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.