US 12,453,129 B1
Stacked nanosheet device for process and performance optimization
Xi-Wei Lin, Fremont, CA (US); Victor Moroz, Saratoga, CA (US); Zudian Qin, Cupertino, CA (US); and Plamen Asenov Asenov, Glasgow (GB)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Nov. 4, 2022, as Appl. No. 17/981,185.
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method of forming a plurality of gate-all-around (GAA) Field Effect Transistors (FET) on a silicon substrate, the method comprising:
forming a first layer of Silicon Germanium (SiGe) alloy above the silicon substrate;
forming a first layer of silicon nanosheet above the first layer of SiGe alloy;
forming a second layer of SiGe alloy above the first layer of silicon nanosheet;
forming a second layer of silicon nanosheet above the second layer of SiGe alloy; and
performing a reactive ion etch of the silicon nanosheet and SiGe alloy layers so as to form at least first and second tapered pillars of silicon nanosheet and SiGe alloy layers, wherein in each of the first and second tapered pillars a width of the etched first layer of silicon nanosheet is greater than a width of the etched second layer of silicon nanosheet, wherein the first silicon nanosheet layer disposed in the first tapered pillar forms a channel of a first GAAFET, the second silicon nanosheet layer disposed in the first tapered pillar forms a channel of a second GAAFET, the first silicon nanosheet layer disposed in the second tapered pillar forms a channel of a third GAAFET, and the second silicon nanosheet layer disposed in the second tapered pillar forms a channel of a fourth GAAFET.