| CPC H10D 30/6735 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching ends of the first semiconductor layers in the source/drain space;
forming an insulating layer on a sidewall of the source/drain space;
partially etching the insulating layer, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer; and
forming a source/drain epitaxial layer in the source/drain space,
wherein after the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.
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