US 12,453,123 B2
Transistor with front-side and back-side contacts and routing
Abhishek A. Sharma, Hillsboro, OR (US); Wilfred Gomes, Portland, OR (US); and Mauro J. Kobrinsky, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,384.
Prior Publication US 2022/0416034 A1, Dec. 29, 2022
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6729 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a support structure having a face extending in a first direction and in a second direction perpendicular to the first direction;
a channel material having a longitudinal structure;
a first source or drain (S/D) region enclosing a first portion of the channel material, the first S/D region having a first face parallel to the face of the support structure and a second face opposite the first face;
a gate electrode enclosing a second portion of the channel material, the gate electrode having a first face that is coplanar with the first face of the first S/D region and a second face that is coplanar with the second face of the S/D region;
a second S/D region enclosing a third portion of the channel material, the second portion between the first portion and the third portion;
a first S/D contact coupled to the first S/D region on the first face; and
a second S/D contact coupled to the first S/D region on the second face.