| CPC H10D 30/65 (2025.01) [H10D 30/0281 (2025.01); H10D 62/116 (2025.01); H10D 62/157 (2025.01)] | 16 Claims |
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1. An HV device, comprising:
a gate dielectric layer, wherein the gate dielectric layer is formed in a first trench, wherein the first trench is formed by etching a semiconductor substrate, and wherein a top surface of the gate dielectric layer is configured to be flush with a top surface of the semiconductor substrate;
a gate conductive material layer, formed on the top surface of the gate dielectric layer;
a first high voltage well region, wherein the first high voltage well region is formed on the semiconductor substrate and is doped with a second conductivity type of impurity;
a drain structure, wherein the drain structure is formed in the first high voltage well region outside a first side face of the gate dielectric layer;
a source structure, wherein the source structure is formed in the first high voltage well region outside a second side face of the gate dielectric layer;
wherein the drain structure comprises a drain high voltage diffusion region doped with a first conductivity type of impurity, a drain shallow trench isolation, a second dielectric layer, and a drain region heavily doped with the first conductivity type of impurity;
wherein the drain high voltage diffusion region is formed in the first high voltage well region, and wherein the drain shallow trench isolation is formed in a selected region of the drain high voltage diffusion region;
a second trench, wherein the second trench is formed in the drain high voltage diffusion region between a second side face of the drain shallow trench isolation and a first side face of the first trench, and wherein the second dielectric layer is formed in the second trench;
wherein the second side face of the drain shallow trench isolation is aligned with a first side face of the second trench; wherein a second side face of the second trench is aligned with the first side face of the first trench; wherein a depth of the drain shallow trench isolation is greater than a depth of the first trench;
wherein the depth of the first trench is equal to a depth of the second trench, and wherein the first trench and the second trench connect with each other to form an overall trench; wherein a bottom surface of the second dielectric layer and a bottom surface of the gate dielectric layer are flush with each other; wherein a first side face of the gate conductive material layer extends to a surface of the second dielectric layer, such that a region covered by the gate conductive material layer has no sharp corner and is away from a bottom sharp corner of the drain shallow trench isolation;
wherein the drain region is formed in a surface region of the drain high voltage diffusion region outside a first side face of the drain shallow trench isolation, and wherein a junction depth of the drain region is less than a thickness of the second dielectric layer;
wherein the source structure comprises a source high voltage diffusion region and a source region heavily doped with the first conductivity type of impurity, wherein the source high voltage diffusion region is formed in the first high voltage well region, and wherein the source region is formed in a surface region of the source high voltage diffusion region; and wherein the first side face of the gate dielectric layer extends into the drain high voltage diffusion region, and wherein the second side face of the gate dielectric layer extends into the source high voltage diffusion region; and wherein a channel region includes the first high voltage well region at a bottom of the gate dielectric layer.
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