US 12,453,119 B2
Gallium oxide semiconductor structure, vertical gallium oxide-based power device, and preparation method
Xin Ou, Shanghai (CN); Wenhui Xu, Shanghai (CN); Tiangui You, Shanghai (CN); and Zhenghao Shen, Shanghai (CN)
Assigned to SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES, Shanghai (CN)
Appl. No. 17/779,573
Filed by SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES, Shanghai (CN)
PCT Filed Nov. 3, 2020, PCT No. PCT/CN2020/126024
§ 371(c)(1), (2) Date May 25, 2022,
PCT Pub. No. WO2021/103953, PCT Pub. Date Jun. 3, 2021.
Claims priority of application No. 201911174463.9 (CN), filed on Nov. 26, 2019.
Prior Publication US 2023/0127051 A1, Apr. 27, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H10D 30/60 (2025.01); H10D 30/63 (2025.01); H10D 62/10 (2025.01); H10D 62/82 (2025.01); H10D 62/832 (2025.01)
CPC H10D 30/63 (2025.01) [H01L 21/02002 (2013.01); H10D 30/611 (2025.01); H10D 62/105 (2025.01); H10D 62/82 (2025.01); H10D 62/8325 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A method for preparing a gallium oxide semiconductor structure, comprising the following steps:
providing a gallium oxide single crystal wafer, wherein a surface of the gallium oxide single crystal wafer is a polished surface;
providing a heterogeneous substrate, wherein a surface of the heterogeneous substrate is a polished surface;
bonding the polished surface of the gallium oxide single crystal wafer to the polished surface of the heterogeneous substrate;
thinning the gallium oxide single crystal wafer to obtain a gallium oxide layer and obtain a composite structure comprising the heterogeneous substrate and the gallium oxide layer stacked in sequence;
treating a top surface of the gallium oxide layer, wherein the top surface of the gallium oxide layer is facing away from the polished surface of the heterogeneous substrate; and
forming a heavily doped gallium oxide layer on the top surface of the gallium oxide layer by performing an ion implantation on the gallium oxide layer, thereby obtaining the gallium oxide semiconductor structure comprising the heterogeneous substrate, the gallium oxide layer, and the heavily doped gallium oxide layer stacked in sequence;
wherein a carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, wherein the carrier concentration of the gallium oxide layer is in a range of 1×1016/cm3 to 9×1017/cm3, and the carrier concentration of the heavily doped gallium oxide layer is greater than 1×1019/cm3.