US 12,453,118 B2
Inter-layer dielectrics and etch stop layers for transistor source/drain regions
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2022, as Appl. No. 17/885,154.
Application 17/885,154 is a division of application No. 17/145,550, filed on Jan. 11, 2021, granted, now 11,522,062.
Claims priority of provisional application 63/082,537, filed on Sep. 24, 2020.
Claims priority of provisional application 63/065,571, filed on Aug. 14, 2020.
Prior Publication US 2022/0384593 A1, Dec. 1, 2022
Int. Cl. H10D 30/62 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H10D 30/6219 (2025.01) [H01L 21/02164 (2013.01); H01L 21/02247 (2013.01); H01L 21/02271 (2013.01); H01L 21/02323 (2013.01); H01L 21/02329 (2013.01); H01L 21/02337 (2013.01); H01L 21/0234 (2013.01); H01L 21/02348 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/021 (2025.01); H10D 64/671 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate structure over a substrate;
a gate spacer adjacent the gate structure;
a source/drain region adjacent the gate spacer;
a first inter-layer dielectric on the source/drain region, the first inter-layer dielectric having a first concentration of an impurity;
a second inter-layer dielectric on the first inter-layer dielectric, the second inter-layer dielectric having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second inter-layer dielectric and the gate spacer being coplanar; and
a source/drain contact extending through the second inter-layer dielectric and the first inter-layer dielectric, the source/drain contact coupled to the source/drain region.
 
7. A device comprising:
a gate structure over a substrate;
a source/drain region adjacent the gate structure;
a gate spacer between the source/drain region and the gate structure, the gate spacer comprising a first spacer layer and a second spacer layer, the first spacer layer proximate the gate structure, the first spacer layer comprising silicon oxycarbonitride having a first atomic percent of nitrogen, the second spacer layer proximate the source/drain region, the second spacer layer comprising silicon oxycarbonitride having a second atomic percent of nitrogen, the first atomic percent greater than the second atomic percent;
an etch stop layer on a sidewall of the gate spacer and a top surface of the source/drain region, the etch stop layer comprising silicon nitride having a third atomic percent of nitrogen, the third atomic percent greater than the first atomic percent;
a first inter-layer dielectric on the etch stop layer; and
a source/drain contact extending through the first inter-layer dielectric and the etch stop layer, the source/drain contact coupled to the source/drain region.
 
13. A device comprising:
a gate structure on a channel region;
a gate spacer adjacent the gate structure, the gate spacer having a first nitrogen concentration;
a source/drain region adjacent the gate spacer;
an etch stop layer on the source/drain region, the etch stop layer having a second nitrogen concentration, the second nitrogen concentration greater than the first nitrogen concentration;
a first inter-layer dielectric on the etch stop layer, the first inter-layer dielectric having a first impurity concentration that increases through the first inter-layer dielectric in a direction extending from a top of the first inter-layer dielectric to a bottom of the first inter-layer dielectric; and
a source/drain contact extending through the first inter-layer dielectric and the etch stop layer, the source/drain contact coupled to the source/drain region.