US 12,453,114 B2
Semiconductor transistor devices having double-sided interconnect structures
Yi-Hsun Chiu, Zhubei (TW); Ching-Wei Tsai, Hsinchu (TW); Yu-Xuan Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Shang-Wen Chang, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 9, 2024, as Appl. No. 18/766,867.
Application 18/766,867 is a continuation of application No. 18/358,140, filed on Jul. 25, 2023, granted, now 12,080,713.
Application 18/358,140 is a continuation of application No. 17/733,169, filed on Apr. 29, 2022, granted, now 11,810,917, issued on Nov. 7, 2023.
Application 17/733,169 is a continuation of application No. 16/944,025, filed on Jul. 30, 2020, granted, now 11,342,326, issued on May 24, 2022.
Claims priority of provisional application 63/016,391, filed on Apr. 28, 2020.
Prior Publication US 2024/0363626 A1, Oct. 31, 2024
Int. Cl. H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01)
CPC H10D 30/6211 (2025.01) [H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first semiconductor channel structure;
a second semiconductor channel structure;
a first gate structure on opposing sides of the first semiconductor channel structure in a first cross-sectional view;
a second gate structure on opposing sides of the second semiconductor channel structure in the first cross-sectional view;
a first source/drain region adjacent the first semiconductor channel structure in a second cross-sectional view perpendicular to the first cross-sectional view;
a second source/drain region adjacent the second semiconductor channel structure in the second cross-sectional view;
a first interconnect structure on a first side of the first gate structure and the second gate structure; and
a second interconnect structure on a second side of the first gate structure and the second gate structure, the second interconnect structure comprising:
a first dielectric layer; and
a contact extending through the first dielectric layer to the first source/drain region, wherein the first dielectric layer extends between the first gate structure and the second gate structure in the first cross-sectional view.