| CPC H10D 30/025 (2025.01) [H10B 12/0335 (2023.02); H10B 12/488 (2023.02)] | 11 Claims |
|
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming a functional stack on the base, wherein the functional stack comprises a first doped layer, a second doped layer and a third doped layer that are stacked sequentially, the first doped layer is provided on the base, dopant ions in the second doped layer are different from dopant ions in the first doped layer, and the dopant ions in the first doped layer are the same as dopant ions in the third doped layer; and
removing a part of the functional stack to form a plurality of active pillars arranged at intervals, wherein the first doped layer in the active pillar serves as a first doped region, the second doped layer in the active pillar serves as a channel region, and the third doped layer in the active pillar serves as a second doped region;
after the providing a base, and before the forming a functional stack on the base, further comprising:
forming a first conductive layer on the base by in-situ doping, wherein the first conductive layer is configured to form a bit line of the semiconductor structure, a material of the first conductive layer comprises germanium, dopant ions are provided in the first conductive layer, and a type of the dopant ions in the first conductive layer is the same as a type of the dopant ions in the first doped layer;
after the forming a functional stack on the base, and before the removing a part of the functional stack, further comprising:
forming a protective layer on the functional stack; and
forming, on the protective layer, a first mask layer with a first mask pattern, the first mask pattern comprising a plurality of first mask bumps and a first mask opening between adjacent ones of the first mask bumps;
wherein the removing a part of the functional stack to form a plurality of active pillars arranged at intervals comprises:
removing the protective layer, the functional stack, the first conductive layer and a part of the base that are exposed in the first mask opening to form a first trench, wherein the remaining functional stack forms a plurality of active strips arranged at intervals, each of the active pillars extends along a first direction, and the remaining first conductive layer forms a conductive strip;
forming a first initial dielectric layer in the first trench, the first initial dielectric layer filling up the first trench;
forming, on the remaining protective layer and the first initial dielectric layer, a second mask layer with a second mask pattern, wherein the second mask pattern comprises a plurality of second mask bumps and a second mask opening between adjacent ones of the second mask bumps, the second mask bump extends along a second direction, and the second direction is perpendicular to the first direction; and
removing the active strip, a part of the first initial dielectric layer and a part of the conductive strip that are exposed in the second mask opening to form a second trench, wherein the second trench extends along the second direction, the remaining active strips form the plurality of active pillars arranged at intervals, the remaining first initial dielectric layer forms a first dielectric layer, the remaining conductive strips form a plurality of bit lines arranged at intervals, and each of the bit lines extends along the first direction.
|