US 12,453,110 B2
Semiconductor device
Norihiro Komiyama, Matsumoto (JP); Masahiro Sasaki, Azumino (JP); Yuichi Onozawa, Matsumoto (JP); and Shoji Yamada, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Mar. 22, 2023, as Appl. No. 18/188,452.
Application 18/188,452 is a continuation of application No. PCT/JP2022/017660, filed on Apr. 13, 2022.
Claims priority of application No. 2021-071267 (JP), filed on Apr. 20, 2021.
Prior Publication US 2023/0231043 A1, Jul. 20, 2023
Int. Cl. H10D 12/00 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01)
CPC H10D 12/481 (2025.01) [H10D 62/126 (2025.01); H10D 62/393 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type;
a first main terminal provided above the upper surface;
a second main terminal provided below the lower surface;
a control terminal configured to control whether or not to cause a current to flow between the first main terminal and the second main terminal; and
a buffer region provided between the drift region and the lower surface and having a higher doping concentration than the drift region, wherein
in a C-V characteristic curve indicating a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal, the C-V characteristic curve has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more.