US 12,453,104 B2
Semiconductor package and method of manufacturing the semiconductor package
Keunho Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 3, 2023, as Appl. No. 18/178,235.
Claims priority of application No. 10-2022-0073290 (KR), filed on Jun. 16, 2022.
Prior Publication US 2023/0413585 A1, Dec. 21, 2023
Int. Cl. H10B 80/00 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01)
CPC H10B 80/00 (2023.02) [H01L 21/561 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92165 (2013.01); H01L 2224/92247 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a chip stack structure on the package substrate, the chip stack structure comprising a base chip having a first thickness, and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness; and
a sealing member on an upper surface of the package substrate and on the chip stack structure;
wherein at least one of the plurality of upper chips comprises:
a chip substrate having opposite first and second surfaces;
a circuit layer on the first surface; and
a stress compensation layer on the second surface, wherein the stress compensation layer has an internal stress that offsets a warpage of the chip substrate.