US 12,453,098 B2
Three-dimensional memory devices
Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); Sheng-Chen Wang, Hsinchu (TW); Feng-Cheng Yang, Zhudong Township (TW); Yu-Ming Lin, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 8, 2024, as Appl. No. 18/406,745.
Application 17/818,562 is a division of application No. 17/140,888, filed on Jan. 4, 2021, granted, now 11,527,553, issued on Dec. 13, 2022.
Application 18/406,745 is a continuation of application No. 17/818,562, filed on Aug. 9, 2022, granted, now 11,910,616.
Claims priority of provisional application 63/058,619, filed on Jul. 30, 2020.
Prior Publication US 2024/0164109 A1, May 16, 2024
Int. Cl. H10B 51/20 (2023.01); H01L 23/535 (2006.01); H10B 51/00 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 64/23 (2025.01)
CPC H10B 51/20 (2023.02) [H01L 23/535 (2013.01); H10B 51/00 (2023.02); H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10D 64/252 (2025.01); H10D 64/258 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first conductive line extending in a first direction;
a ferroelectric layer on a sidewall of the first conductive line;
a semiconductor layer on a sidewall of the ferroelectric layer;
a first dielectric layer on a sidewall of the semiconductor layer; and
a second conductive line having a first main region and a first extension region, the first main region contacting the semiconductor layer, the first extension region separated from the semiconductor layer by the first dielectric layer, the second conductive line extending in a second direction, the second direction perpendicular to the first direction.