US 12,453,097 B2
Semiconductor device and memory device including a dummy element
Changbum Kim, Seoul (KR); and Sunghoon Kim, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 2, 2021, as Appl. No. 17/453,228.
Claims priority of application No. 10-2021-0044702 (KR), filed on Apr. 6, 2021.
Prior Publication US 2022/0320131 A1, Oct. 6, 2022
Int. Cl. H10B 43/50 (2023.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/50 (2023.02) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region, wherein a longest dimension of the gate structure extends in a first direction that is parallel to an upper surface of the substrate; and
at least one dummy element disposed between a pair of semiconductor elements, of the plurality of semiconductor elements, in a second direction, intersecting the first direction,
wherein the at least one dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and wherein a longest dimension of the dummy gate structure extends in the first direction,
wherein the active region includes a first active region and a second active region, and the gate structure is disposed between the first active region and the second active region in the second direction,
wherein the dummy active region includes a first dummy active region and a second dummy active region, and the dummy gate structure is disposed between the first dummy active region and the second dummy active region,
wherein a length of each of the first dummy active region and the second dummy active region, in the second direction, is less than a length of each of the first active region and the second active region included in each of the pair of semiconductor elements,
wherein the second direction is a horizontal direction parallel to the upper surface of the substrate, and
wherein an entire length of the dummy active region, in the first direction, is greater than or equal to an entire length of the active region included in at least one of the pair of semiconductor elements.