| CPC H10B 43/35 (2023.02) [H01L 21/0337 (2013.01); H10B 43/50 (2023.02); H10D 30/699 (2025.01); H10D 62/115 (2025.01); H10D 64/037 (2025.01)] | 20 Claims |
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1. A method for manufacturing an integrated circuit (IC), the method comprising:
forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate;
filling an isolation material in the isolation trench and the logic device trench;
removing the isolation material from the logic device trench, wherein the isolation material is kept in the isolation trench to form an isolation structure; and
forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench;
forming a second logic device comprising a second logic gate electrode separated from the substrate by a second logic gate dielectric; and
forming first and second source/drain regions in the substrate on opposite sides of the logic device trench,
wherein the second logic gate dielectric is formed on an upper surface of the substrate higher than the logic device trench.
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