US 12,453,093 B2
Memory circuitry and method used in forming memory circuitry
Andrew Li, Boise, ID (US); Sidhartha Gupta, Boise, ID (US); and Adam W. Saxler, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 20, 2022, as Appl. No. 17/948,521.
Prior Publication US 2024/0098993 A1, Mar. 21, 2024
Int. Cl. H01L 27/11582 (2017.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] 36 Claims
OG exemplary drawing
 
1. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier, the stack comprising laterally-spaced memory-block regions;
forming channel-material strings that extend through the first and second tiers in the memory-block regions, the channel-material strings directly electrically coupling to conductor material of the conductor tier at least in a finished-circuitry construction; and
forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions, the intervening material in the finished-circuitry construction comprising:
a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-block regions, the laterally-outer insulative lining having its lowest surface between a top and a bottom of the lowest first tier in the finished-circuitry construction, the laterally-outer insulative lining having its highest surface at or below a lowest surface of the next-lowest first tier in the finished-circuitry construction;
laterally-inner insulating material extending the immediately-laterally-adjacent longitudinally-along memory-block regions laterally-inward of the laterally-outer insulative lining; and
an interface between the laterally-outer insulative lining and the laterally-inner insulating material.