	US 12,453,090 B2
	Three-dimensional semiconductor memory device
Sanghoon Lee, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 10, 2022, as Appl. No. 17/668,773.
Application 17/668,773 is a continuation of application No. 16/927,044, filed on Jul. 13, 2020, granted, now 11,251,197, issued on Feb. 15, 2022.
Claims priority of application No. 10-2019-0137329 (KR), filed on Oct. 31, 2019.
Prior Publication US 2022/0165750 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/10 (2006.01); H01L 23/522 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)

CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 43/10 (2023.02); H10B 43/40 (2023.02)]

19 Claims

1. A semiconductor device, comprising:

a substrate structure;

a lower structure on the substrate structure;

an upper pattern on the lower structure;

a stacked structure on the lower structure;

separation structures passing through the stacked structure; and

a vertical structure between the separation structures, passing through the stacked structure, the upper pattern and the lower structure, and comprising a channel layer,

wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked,

the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern,

the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure,

an upper surface of the second portion contacts a lower surface of the upper pattern,

a lowermost end of the channel layer is at a lower level than a lowermost end of the first portion of the first lower pattern;

wherein the first portion, the second portion, the third portion, and the upper pattern comprise polysilicon,

wherein the second lower pattern comprises a material different from the polysilicon, and

wherein a lowermost gate layer among the plurality of gate layers is spaced apart from the upper pattern.

12. A semiconductor device, comprising:

a lower structure on a substrate;

an upper pattern on the lower structure and the substrate;

a stacked structure on the lower structure;

a vertical structure passing through the stacked structure, the upper pattern and the lower structure; and

a separation structure passing through the stacked structure, the upper pattern and the lower structure and spaced apart from the vertical structure,

wherein the upper pattern comprises

an upper portion parallel to an upper surface of the substrate and

a support portion of the upper pattern, the support portion extending from the upper portion between the substrate and the stacked structure and in direct contact with the substrate,

the lower structure is between the upper portion of the upper pattern and directly on the substrate,

the separation structure comprises a first separation portion passing through the stacked structure, the upper portion of the upper pattern and the lower structure, and a second separation portion passing through the stacked structure and in contact with the support portion of the upper pattern,

the stacked structure comprises a plurality of gate layers stacked spaced apart in a direction perpendicular to the upper surface of the substrate,

the vertical structure comprises a channel layer passing through a plurality of gate layers, the upper portion of the upper pattern, and the lower structure,

the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern,

an upper surface of the second portion contacts a lower surface of the upper pattern,

a lower end of the channel layer is at a lower level than a lower end of the first lower pattern,

a lowermost gate layer among the plurality of gate layers is spaced apart from the upper pattern, and

the upper portion and the support portion of the upper pattern are at a lower level than the lowermost gate layer among the plurality of gate layers.

15. A semiconductor device, comprising:

a lower structure including a first lower pattern;

an upper pattern on the lower structure;

a stacked structure on the upper pattern;

a vertical structure passing through the stacked structure, the lower structure and the upper pattern; and

a separation structure passing through the stacked structure, the upper pattern and the lower structure and spaced apart from the vertical structure,

wherein the stacked structure comprises a plurality of gate layers spaced apart in a vertical direction perpendicular to an upper surface of the lower structure while being stacked,

wherein the vertical structure comprises:

an insulating core region;

a channel layer on a side surface of the insulating core region; and

a dielectric structure on an external side surface of the channel layer and including a data storage material layer,

wherein the first lower pattern comprises:

a first portion penetrating through the dielectric structure and contacting the channel layer;

a second portion extending from an upper region of the first portion in a horizontal direction and contacting a lower surface of the upper pattern; and

a third portion extending from a lower region of the first portion in the horizontal direction,

wherein the horizontal direction is perpendicular to the vertical direction,

wherein at least a portion of the third portion is spaced apart from the second portion in the vertical direction.