| CPC H10B 12/50 (2023.02) | 18 Claims |
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1. A semiconductor package, comprising:
a first semiconductor chip;
second semiconductor chips sequentially stacked on the first semiconductor chip;
for each second semiconductor chip, a front connection pad on a lower surface of the second semiconductor chip;
for each semiconductor chip of the first semiconductor chip and the second semiconductor chips, a rear connection pad attached to an upper surface of the semiconductor chip, wherein each rear connection pad faces a corresponding front connection pad;
for each rear connection pad and corresponding front connection pad, a chip connection terminal between the front connection pad and the rear connection pad; and
a support structure between the first semiconductor chip and one of the second semiconductor chips, and support structures between adjacent ones of the second semiconductor chips, each support structure:
being spaced apart from the front connection pads, the rear connection pads, and the chip connection terminals,
having a vertical height greater than a vertical height of the chip connection terminals, and
including a metal,
wherein the support structures are electrically isolated from active circuitry in the first semiconductor chip and the second semiconductor chips,
wherein each support structure includes:
a first support post attached to the lower surface of the corresponding second semiconductor chip, and
a second support post attached to the upper surface of the first semiconductor chip or to the upper surface of a corresponding one of the second semiconductor chips, the upper surface of each second semiconductor chip being opposite to the lower surface of said second semiconductor chip, and
wherein a lower surface of each first support post contacts an upper surface of the corresponding second support post.
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9. A semiconductor package, comprising:
an interposer;
a first semiconductor chip mounted on the interposer;
second semiconductor chips sequentially stacked on the first semiconductor chip;
for each second semiconductor chip, a front connection pad on a lower surface of the second semiconductor chip;
for each semiconductor chip of the first semiconductor chip and the second semiconductor chips, a rear connection pad attached to an upper surface of the semiconductor chip;
for each rear connection pad and corresponding front connection pad, a chip connection terminal between the front connection pad and the rear connection pad;
a support structure between the first semiconductor chip and one of the second semiconductor chips, and support structures between adjacent ones of the second semiconductor chips, each support structure being formed of a metal and including:
a first support post attached to the lower surface of the corresponding second semiconductor chip, and
a second support post attached to the upper surface of the first semiconductor chip or to the upper surface of a corresponding one of the second semiconductor chips, the upper surface of each second semiconductor chip being opposite to the lower surface of said second semiconductor chip;
an insulating adhesive layer between the first semiconductor chip and one of the second semiconductor chips, and insulating adhesive layers between adjacent ones of the second semiconductor chips, each insulating adhesive layer:
surrounding the corresponding chip connection terminal and the corresponding support structure, and
having a thickness substantially equal to a thickness of the corresponding support structure; and
a molding layer on the first semiconductor chip and surrounding the second semiconductor chips and the insulating adhesive layers,
wherein each support structure is electrically isolated from active circuitry in the first semiconductor chip and the second semiconductor chips, and
wherein, for each support structure, a lower surface of the first support post contacts an upper surface of the second support post.
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16. A semiconductor package, comprising:
a redistribution layer (RDL) interposer;
a buffer chip including a first substrate, first through electrodes penetrating at least a portion of the first substrate, and a first wiring layer on an active surface of the first substrate and including first wiring patterns, first wiring vias, and a first inter-wiring insulating layer surrounding the first wiring patterns and the first wiring vias, the buffer chip being attached to the RDL interposer with the active surface of the first substrate facing the RDL interposer;
memory cell chips, each of which includes a second substrate, second through electrodes penetrating at least a portion of the second substrate, and a second wiring layer on an active surface of the second substrate and including second wiring patterns, second wiring vias, and a second inter-wiring insulating layer surrounding the second wiring patterns and the second wiring vias, each memory cell chip being sequentially stacked on the buffer chip with the active surface of the second substrate of each memory chip facing the buffer chip;
for each memory cell chip, front connection pads attached to a lower surface of the second wiring layer;
for each substrate of the first substrate and the second substrates, rear connection pads attached to an inactive surface of the substrate;
for each rear connection pad and corresponding front connection pad, a chip connection terminal between the corresponding front connection pad and the rear connection pad;
a support structure between the buffer chip and one of the memory cell chips, and support structures between adjacent ones of the memory cell chips, each support structure being formed of a metal and including a first support post spaced apart from a corresponding front connection pad and contacting corresponding second wiring patterns, and a second support post spaced apart from a corresponding rear connection pad and contacting some of the corresponding second through electrodes;
an insulating adhesive layer between the buffer chip and one of the memory cell chips, and insulating adhesive layers between adjacent ones of the memory cell chips, each insulating layer surrounding corresponding chip connection terminals and corresponding support structures, each insulating adhesive layer having a thickness substantially equal to a thickness of each of the support structures; and
a molding layer on the buffer chip and surrounding the memory cell chips and the insulating adhesive layers,
wherein the support structures are electrically isolated from active circuitry in the buffer chip and the memory cell chips,
wherein, for each support structure, a lower surface of the first support post of the support structure contacts an upper surface of the second support post of the support structure.
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